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Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
FEATURES
* * * * * * * * * Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps. 2.5V or 3.3V Supply range. Enhanced DDR and SDRAM Output Drive selected by I2C. Available in 56 pin SSOP.
PIN CONFIGURATION
FBOUT VDD3.3_2.5 GND DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 VDD3.3_2.5 GND DDR2T_SDRAM2 DDR2C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR3T_SDRAM4 DDR3C_SDRAM5 VDD3.3_2.5 GND DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 VDD3.3_2.5 SDATA GND VDD2.5 DDR12T DDR12C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SEL_DDR VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK VDD2.5 GND DDR13C DDR13T
PLL103-53
Note: #: Active Low
BLOCK DIAGRAM
DESCRIPTIONS
The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-53 can be used in conjunction with the PLL202-14/-54 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-53 also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up).
DDR0T_SDRAM10 SDATA SCLK I2C Control DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 DDR2T_SDRAM2 DDR2C_SDRAM3 DDR3T_SDRAM4 DDR3C_SDRAM5 DDR4T_SDRAM6 BUF_IN DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 DDR(6:13)T DDR(6:13)C FBOUT PD#
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 1
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
PIN DESCRIPTIONS
Name
FBOUT BUF_IN PD
Number
1 13 44
Type
O I I
Description
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V. Reference input from chipset. 3.3V input for STANDARD SDRAM mode; 2.5V input for DDR-ONLY mode. Power Down Control input. When low, it will tri-state all outputs.
SEL_DDR
56
I
Input configure for DDR-ONLY mode or STANDARD SDR mode. 1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V); 0 = SDR mode (when VDD3.3_2.5 select 3.3V). In DDR-ONLY mode, all outputs will be configured as DDR outputs. In STANDARD SDR mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21 and 22 will be configured as STANDARD SDR outputs, and pin 27, 28, 29, 30, 35, 36, 37, 38, 41, 42, 46, 47, 50, 51,52 and 53 will be configured as DDR outputs.
These outputs provide True copies of BUF_IN. These outputs provide complementary copies of BUF_IN. When SEL_DDR=1, these outputs provide DDR mode outputs; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends on VDD3.3_2.5. When SEL_DDR=1, these outputs provide complementary copies of BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends on VDD3.3_2.5. When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected. 2.5V power supply. Ground.
DDR[6:13]T DDR[6:13]C DDR[0,1:5]T_SDRA M [10,0,2,4,6,8] DDR[0,1:5]C_SDRA M [11,1,3,5,7,9] VDD3.3_2.5 VDD2.5 GND
36,38,42,47, 51,53,27,29 35,37,41,46, 50,52,28,30 4,6,10,15, 19,21 5,7,11,16, 20,22 2,8,12,17,23 32,40,45, 49,55 3,9,14,18, 25,31,34,39, 43,48,54
O O O
O P P P
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 2
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
I2C BUS CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _
Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5
Pin#
56 -
Default
1 0 0
Description
SEL_DDR ( I2C is ready only, value is set through pin56 ) SDRAM Drive. DDR Drive. Bit6 Bit5 0 1 1 DDR Drive Enhanced 25% Normal Normal SDRAM Drive Enhanced 25% Normal Enhanced 25% X 0 1
Enhance Drive Control
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
27,28,29,30 53, 52 51, 50 47, 46 42, 41
1 1 1 1 1
DDR12T, DDR12C, DDR13T, DDR13C DDR11T, DDR11C DDR10T, DDR10C DDR9T, DDR9C DDR8T, DDR8C
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 3
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
2. BYTE 7: Outputs Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
38, 37 36, 35 21, 22 19, 20 15, 16 10, 11 6, 7 4, 5
Default
1 1 1 1 1 1 1 1
Description
DDR7T, DDR7C DDR6T, DDR6C DDR5T_SDRAM8, DDR5C_SDRAM9 DDR4T_SDRAM6, DDR4C_SDRAM7 DDR3T_SDRAM4, DDR3C_SDRAM5 DDR2T_SDRAM2, DDR2C_SDRAM3 DDR1T_SDRAM0, DDR1C_SDRAM1 DDR0T_SDRAM10, DDR0C_SDRAM11
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 4
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature ESD Voltage
SYMBOL
V DD VI VO TS TA
MIN.
V SS -0.5 V SS -0.5 V SS -0.5 -65 0
MAX.
7.0 V DD +0.5 V DD +0.5 150 70 2
UNITS
V V V C C KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions PARAMETERS
Supply Voltage Supply Voltage Input Capacitance Output Capacitance
SYMBOL
V DD3.3 V DD2.5 CIN COUT
MIN.
3.135 2.375
MAX.
3.465 2.625 5 6
UNITS
V V pF pF
3. Electrical Specifications PARAMETERS
Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Output High Current Output Low Current
Note: TBM: To be measured
SYMBOL
V IH V IL I IH I IL V OH V OL I OH I OL
CONDITIONS
All Inputs except I2C All inputs except I2C V IN = V DD V IN = 0 IOL = -12mA, IOL = 12mA, VDD = 2.375V VDD = 2.375V
MIN.
2.0 VSS-0.3
TYP.
MAX.
VDD+0.3 0.8 TBM TBM
UNITS
V V uA uA V
1.7 0.6 -18 26 -32 35
V mA mA
VDD = 2.375V, VOUT=1V VDD = 2.375V, VOUT=1.2V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 5
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
3. Electrical Specifications (Continued) PARAMETERS
Supply Current (DDR-only mode) Supply Current (SDRAM mode) Supply Current Output Crossing Voltage Output Voltage Swing Duty Cycle Max. Operating Frequency Rising Edge Rate Falling Edge Rate Clock Skew ( pin to pin ) Stabilization Time
Note: TBM: To be measured
SYMBOL
IDD IDD IDDS VOC VOUT DT
CONDITIONS
Unloaded outputs, 133MHz Unloaded outputs, 133MHz PD = 0
MIN.
TYP.
MAX.
TBM TBM TBM
UNITS
mA mA mA V V % MHz V/ns V/ns ps ms
(VDD/2) -0.1 1.1 Measured @ 1.5V 45 66
VDD/2
(VDD/2)+ 0.1 VDD-0.4
50
55 170
TOR TOF TSKEW TST
Measured @ Measured @
0.4V ~ 2.4V 2.4V ~ 0.4V
1.0 1.0
1.5 1.5
2.0 2.0 100 0.1
All outputs equally loaded
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 6
Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
PACKAGE INFORMATION
0.395 - 0.420 10.033 - 10.668
0.291 - 0.299 7.391 - 7.595
0.008 - 0.0135 0.203 - 0.343
0.025 0.635
0.015 (0.381) 0.010 - 0.016 (0.254 - 0.406) 45 0 0.720 - 0.730 (18.288 - 18.542)
0.087 - 0.094 (2.210 - 2.388)
0.095 - 0.110 (2.413 - 2.794) 30-6 0 0.050 MIN (1.270) 0.008 - 0.016 (0.203 - 0.406)
56PIN SSOP
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL103-53 X C
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 7

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